Q J Example CLK Determine the Q output for the J-K flip-flop, given the inputs shown. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge). In addition to the clock input, it has two inputs, labeled J and K. (a) Positive-edge triggered (b) Negative-edge triggeredġ2 Summary Flip-flops The J-K flip-flop is more versatile than the D flip flop. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. Dynamic input indicatorġ1 Summary Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock otherwise it is latched. The active edge can be positive or negative. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. Q Notice that the Enable is not active during these times, so the output is latched.ġ0 Summary Flip-flops A flip-flop differs from a latch in the manner it changes states. Q D Example EN Determine the Q output for the D latch, given the inputs shown. If EN is LOW, then there is no change in the output and it is latched. S R EN Qħ Summary Latches The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D Q Q D EN EN Q Q A simple rule for the D latch is: Q follows D when the Enable is active.Ĩ Summary Latches The truth table for the D latch summarizes its operation. Q R Solution Keep in mind that S and R are only active when EN is HIGH. S Q EN Example Show the Q output with relation to the input signals. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. 1Q S-R latches are frequently used for switch debounce circuits as shown: 2Q Position 1 to 2 Position 2 to 1 S R Q VCC 3Q S 4Q R 74LS279AĪ gated latch is a variation on the basic latch. To SET any of the latches, the S line is pulsed low. It features four internal latches with two having two S inputs. 1 Q 1 Rĥ Summary Latches The active-LOW S-R latch is available as the 74LS279A IC.
1 S 1 Q Latch initially SET Never apply an active set and reset at the same time (invalid). 1 S 1 Q Latch initially RESET 1 Q 1 R To RESET the latch a momentary LOW is applied to the R input while S is HIGH.
To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). Latch initially SET 1Ĥ Summary Latches The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. Latch initially RESET 1 R S Q 1 To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. R S Q 1 Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0).
R S Q Q Q Q S R NOR Active-HIGH Latch NAND Active-LOW Latchģ Summary Latches The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW. With NOR gates, the latch responds to active-HIGH inputs with NAND gates, it responds to active-LOW inputs. It can be constructed from NOR gates or NAND gates. The S-R (Set-Reset) latch is the most basic type. Presentation on theme: "Digital Fundamentals Floyd Chapter 7 Tenth Edition"- Presentation transcript:ġ Digital Fundamentals Floyd Chapter 7 Tenth EditionĢ Summary Latches A latch is a temporary storage device that has two stable states (bistable).
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